7805ALP
16-Bit Latchup Protected ADC
Logic Diagram
Memory
F
EATURES
:
• 16-bit organization
• Latchup Protection Technology™
• R
AD
-P
AK
® radiation-hardened against natural space radia-
tion
• Total dose hardness:
- > 50 krads(Si), depending upon space mission
• Latchup converted to reset.
- Rate based on cross section and mission.
• Package:
- 28 pin R
AD
-P
AK
® flat pack
- 28 pin R
AD
-P
AK
® DIP
• 100 kHz min sampling rate
• Standard ± 10V input range
• Advance CMOS technology
- 86 dB min SINAD with 20 kHz input
- Single 5V supply operation
- Utilizes internal or external reference
- Full parallel data output
- Power dissipation: 132 mW max
D
ESCRIPTION
:
Maxwell Technologies’ 7805ALP high-speed analog-to-digital
converter features a greater than 50 krad (Si) total dose toler-
ance, depending upon space mission. Using Mawell’s radia-
tion-hardened R
AD
-P
AK
® packaging technology, the 7805ALP
incorporates the commercial ADS7805 from Burr Brown. This
device is latchup protected by Maxwell Technologies’ LPT™
technology. The 7805ALP, 16-bit sampling CMOS A/D . The
device contains a complete 16-bit capacitor-based SAR A/D
with S/H, reference, clock, interface for microprocessor use,
and three-state output drivers. The 7805ALP is specified at a
100 kHz sampling rate, and guaranteed over the full tempera-
ture range. Laser-trimmed scaling resistors provide an indus-
try-standard ± 10V input range, while the innovative design
allows operation from a single 5V supply, with power dissipa-
tion of under 132 mW.
Maxwell Technologies' patented R
AD
-P
AK
® packaging technol-
ogy incorporates radiation shielding in the microcircuit pack-
age. It eliminates the need for box shielding while providing
the required radiation shielding for a lifetime in orbit or space
mission. In a GEO orbit, R
AD
-P
AK
® provides greater than 50
krad (Si) radiation dose tolerance. This product is available
with screening up to Maxwell Technologies self-defiened
Class K.
01.10.05 Rev 9
All data sheets are subject to change without notice
1
(858) 503-3300 Fax: (858) 503-3301- www.maxwell.com
©2005 Maxwell Technologies
All rights reserved.
16-Bit Latchup Protected ADC
T
ABLE
1. 7805ALP P
INOUT
D
ESCRIPTION
P
IN
N
UMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
N
AME
V
IN
AGND1
REF
CAP
AGND2
D15 (MSB)
D14
D13
D12
D11
D10
D9
D8
DGND
D7
D6
D5
D4
D3
D2
D1
D0 (LSB)
STATUS*
R/C
CS
BUSY
DECPLNG
V
S
0
0
0
0
0
0
0
0
0
I
I
0
0
0
0
0
0
0
0
0
D
IGITAL
I/O
D
ESCRIPTION
Analog input.
Analog ground. Used internally as ground reference point.
Reference input/output. 2.2 µ F tantalum capacitor to ground
7805ALP
Reference buffer capacitor. 2.2 µ F tantalum capacitor to ground.
Analog ground.
Data bit 15. Most Significant Bit (MSB) of conversion results. When STATUS is
HIGH*, D15 must not be driven high.
Data bit 14. When STATUS is HIGH*, D14 must not be driven high.
Data bit 13. When STATUS is HIGH*, D13 must not be driven high.
Data bit 12. When STATUS is HIGH*, D12 must not be driven high.
Data bit 11. When STATUS is HIGH*, D11 must not be driven high.
Data bit 10. When STATUS is HIGH*, D10 must not be driven high.
Data bit 9. When STATUS is HIGH*, D9 must not be driven high.
Data bit 8. When STATUS is HIGH*, D8 must not be driven high.
Digital Ground
Data bit 7. When STATUS is HIGH*, D7 must not be driven high.
Data bit 6. When STATUS is HIGH*, D6 must not be driven high.
Data bit 5. When STATUS is HIGH*, D5 must not be driven high.
Data bit 4. When STATUS is HIGH*, D4 must not be driven high.
Data bit 3. When STATUS is HIGH*, D3 must not be driven high.
Data bit 2. When STATUS is HIGH*, D2 must not be driven high.
Data bit 1. When STATUS is HIGH*, D1 must not be driven high.
Data bit 0. Least Significant Bit (LSB) of conversion results. When STATUS is
HIGH*, D0 must not be driven high.
STATUS when HIGH indicates latchup protection is active and output data is
invalid. Capacitive loading should not exceed 1000 pF.
With CS LOW and BUSY HIGH, a falling edge of R/C initiates a new conversion.
When STATUS is HIGH*, CS and R/C must not be driven high.
Internally OR’d with R/C. If R/C LOW, a falling edge on CS initiates a new conver-
sion. When STATUS is HIGH*, CS and R/C must not be driven high.
At the start of a conversion, BUSY goes LOW and stays LOW until the conversion
is completed and the digital outputs have been updated.
Supply voltage high speed decoupling pin. Decouple to ground with 1.0 µ F ceramic
capacitor.
Supply input. Nominally 5V. Decouple to ground with 10 µ F tantalum capacitor.
Memory
01.10.05 Rev 9
All data sheets are subject to change without notice
2
©2005 Maxwell Technologies
All rights reserved.
16-Bit Latchup Protected ADC
T
ABLE
2. 7805ALP A
BSOLUTE
M
AXIMUM
R
ATINGS
P
ARAMETER
Analog Inputs
S
YMBOL
V
IN
CAP
REF
DGND
AGND1
AGND2
V
S
Θ
JC
--
T
J
--
--
--
M
IN
-25
V
S
9
-0.3
-0.3
-0.3
--
-0.3
T
YP
--
--
--
--
--
--
7
--
7805ALP
M
AX
25
AGND2 - 0.3
--
0.3
0.3
0.3
VS + 0.3
11
825
165
U
NIT
V
Ground Voltage Difference
V
Supply Input
Digital Inputs
Thermal Impedance
Internal Power Dissipation
Maximum Junction Temperature
V
V
°
C/W
mW
°
C
T
ABLE
3. 7805ALP DC A
CCURACY
S
PECIFICATIONS
(V
S
= 5V, T
A
= -40
TO
+85
°
C U
NLESS
O
THERWISE
S
PECIFIED
)
P
ARAMETER
Integral Linearity Error
Differential Linearity Error
No Missing Codes
1
Transition Noise
2
Full Scale Error
3,4
Full Scale Error Drift
Bipolar Zero Error
3
Bipolar Zero Error Drift
Power Supply Sensitivity
1. Guaranteed by design
2. Typical rms noise at worst case transitions and temperatures.
3. Measured with various fixed resistors.
4. Full scale error is worst case - Full Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, divided
by the transition voltage (not divided by the full-scale range) and included the effect of offset error.
4.8V < V
S
< 5.25V
C
ONDITIONS
S
UBGROUPS
M
IN
--
--
15
--
--
--
--
--
--
T
YP
--
--
--
1.3
--
±7
--
±2
--
M
AX
±3
4, -1
--
--
±0.5
--
±10
--
±8
U
NIT
LSB
LSB
Bits
LSB
%
ppm/
°
C
mV
ppm/
°
C
LSB
Memory
T
ABLE
4. 7805ALP D
IGITAL
I
NPUTS
(V
S
= 5V, T
A
= -40
TO
+85
°
C U
NLESS
O
THERWISE
S
PECIFIED
)
P
ARAMETER
V
IL
V
IH
01.10.05 Rev 9
S
UBGROUPS
1, 2, 3
M
IN
-0.3
2.0
T
YP
--
--
M
AX
0.8
V
S
+0.3
U
NIT
V
V
All data sheets are subject to change without notice
3
©2005 Maxwell Technologies
All rights reserved.
16-Bit Latchup Protected ADC
T
ABLE
4. 7805ALP D
IGITAL
I
NPUTS
(V
S
= 5V, T
A
= -40
TO
+85
°
C U
NLESS
O
THERWISE
S
PECIFIED
)
P
ARAMETER
I
IL
, I
IH
S
UBGROUPS
1, 2, 3
M
IN
--
T
YP
--
7805ALP
M
AX
±10
U
NIT
µA
T
ABLE
5. 7805ALP A
NALOG
I
NPUTS
(V
S
= 5V, T
A
= -40
TO
+85
°
C U
NLESS
O
THERWISE
S
PECIFIED
)
P
ARAMETER
Voltage Ranges
1
Impedance
Capacitance
2
1. Tested by application of signal.
2. Guarenteed by design
S
UBGROUPS
1, 2, 3
1, 2, 3
--
M
IN
-10
--
--
T
YP
±10
23
35
M
AX
10
--
--
U
NIT
V
k
Ω
pF
Memory
T
ABLE
6. 7805ALP T
HROUGHPUT
S
PEED
(V
S
= 5V, T
A
= -40
TO
+85
°
C U
NLESS
O
THERWISE
S
PECIFIED
)
P
ARAMETER
Conversion Time
Complete Cycle (Acquire and Convert)
Throughput Rate
1
1. Guaranteed by design
S
UBGROUPS
9, 10, 11
9, 10, 11
M
IN
--
--
100
T
YP
7.6
--
--
M
AX
8
10
--
U
NIT
µs
µs
kHz
T
ABLE
7. 7805ALP AC A
CCURACY
S
PECIFICATIONS
(V
S
= 5V, T
A
= -40
TO
+85
°
C U
NLESS
O
THERWISE
S
PECIFIED
)
P
ARAMETER
Spurious-Free Dynamic Range
1,2
Total Harmonic Distortion
1,2
Signal-to-(Noise + Distortion)
1,2
Signal-to-Noise
1,2
Full-Power Bandwidth
3
1. All specifications in dB are referred to a full-scale 10V input.
2. Guaranteed by design.
3. Full-power bandwidth defined as full-scale input frequency at which signal-to-(noise + distortion) degrades to 60 dB or 10 bits of
accuracy.
01.10.05 Rev 9
T
EST
C
ONDITIONS
f
IN
= 45 kHz
f
IN
= 45 kHz
f
IN
= 45 kHz
-60dB Input
f
IN
= 45 kHz
S
UBGROUPS
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
M
IN
90
--
83
--
83
--
T
YP
--
--
--
30
--
250
M
AX
--
-90
--
--
--
--
U
NIT
dB
dB
dB
dB
kHz
All data sheets are subject to change without notice
4
©2005 Maxwell Technologies
All rights reserved.
16-Bit Latchup Protected ADC
T
ABLE
8. 7805ALP S
AMPLING
D
YNAMICS
(V
S
= 5V, T
A
= -40
TO
+85
°
C U
NLESS
O
THERWISE
S
PECIFIED
)
P
ARAMETER
Aperture Delay
Transient Response
Overvoltage Recovery
1
FS Step
T
EST
C
ONDITIONS
S
UBGROUPS
9, 10, 11
9, 10, 11
9, 10, 11
M
IN
--
--
--
T
YP
40
2
150
7805ALP
M
AX
--
--
--
U
NIT
nS
µS
nS
1. Recovers to specified performance after 2 x f
S
input overvoltage.
T
ABLE
9. 7805ALP R
EFERENCE
T
ABLE
10.
(V
S
= 5V, T
A
= -40
TO
+85
°
C U
NLESS
O
THERWISE
S
PECIFIED
)
P
ARAMETER
Internal Reference Voltage
Internal Reference Source Current (Must use external buffer)
Internal Reference Drift
External Reference Voltage Range for Specified Linearity
1
External Reference Current Drain
2
1. Tested by application of signal.
2. Guaranteed by design
S
UBGROUPS
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
--
M
IN
2.48
--
--
--
--
T
YP
2.5
1
8
2.5
--
M
AX
2.52
--
--
--
100
U
NIT
V
Memory
µA
ppm/
°
C
V
µA
T
ABLE
11. 7805ALP D
IGITAL
O
UTPUTS
(V
S
= 5V, T
A
= -40
TO
+85
°
C U
NLESS
O
THERWISE
S
PECIFIED
)
P
ARAMETER
Data Formatting
Data Coding
V
OL
V
OH
Leakage Current
Output Capacitance
1
1. Guarenteed by design
(I
SINK
= 1.6mA) 4.0
(I
SOURCE
= -400 µ A)
High-Z State, V
OUT
= 0V
to V
S
High-Z State
1, 2, 3
1, 2, 3
1, 2, 3
--
--
4.0
--
--
T
EST
C
ONDITIONS
S
UBGROUPS
M
IN
T
YP
M
AX
U
NIT
(Parallel 16-bits Binary Two’s Complement)
Binary Two’s Complement
--
--
--
10
0.4
--
±5
--
V
V
µA
pF
01.10.05 Rev 9
All data sheets are subject to change without notice
5
©2005 Maxwell Technologies
All rights reserved.
